Ohio University
School of Electrical Engineering and Computer Science
EE4143/5143 Design of Digital Circuits
Course Schedule, Spring 2013

Wk	Date	Subject	Reading	Homework
			Late HW and computer assignments will lower the assignment grade as follows:	1 day late  -10% < 1 week  -25% < 1 month  -50% > 1 month  -75%
1	Jan 14	Class and lab organization, what you will learn Overview of VHDL technology	Download Evita, Evita 1.3 and 2 Entity Architecture
		Introduction to VHDL, package, entity, architecture, names	2.1 - 2.9, VHDL notes, slides 2
		Concurrency, process, delta time, signals	3.1-3.6, Evita 3 signals, slides 3,	Design proposal meeting with TA
2	Jan 21	Martin Luther King holiday	Format for design proposal	Sample design ideas
		Signal and variable assignment, if, case and loop statements	4.1-4.5, slides 4a, Evita 6
		Null statement, Procedure call statement, Return statement	4.6-4.12, slides 4b
3	Jan 28	Assert, and wait statements, process, conditional signal assignment,	5.1-5.2, slides 5, Evita 8	HW 1 due
		Component declaration and instantiation, generate, block,	5.3-5.8
4	Feb 4	Subprogram, package, resolution function, Overloading,	6.1-6.6 slides 6 , Evita 7	HW 2 due
		Return values and type casting, guard,	Evita 4 - Entity, port, generics 6.7-6.8
5	Feb 11	Design unit, generics,	7.1-7.3 slides 7	Design proposals due
		Configuration specification, configuration declaration, library	7.4-7.7, Evita 5
6	Feb 18	A design case, Simulation, writing a test bench, Test bench, design synthesis	11.1-11.6 slides 11 slides 11a Evita 9	HW 3 due
		Files, ROM, bidirectional pads, attribute, access and record types, guarded blocks, signals, disconnection	10.1-10.9 slides 10
7	Feb 25	FSM output, synthesis	9.4-9.5 slides 9	HW 4 due
	Feb 27	Midterm	chapters 1-7 and 10-11	past midterm solution
		Writing VHDL for Synthesis	A VHDL Synthesis Navambi =>
8	March 4	Spring break	Spring break	Spring break
9	March 11	General guidelines, combinatorial synthesis	8.1-8.3, Overview RASP
		Registers, latches, buffers, MUXs, operators	8.4-8.6,
		Simulation vs synthesis, synthesis process	8.7-8.10,slides 8a
10	March 18	Spartan chips, Synthesis	9.1-9.3slides 8b
		Progress and impact of VLSI (ppt)	1.1,1.2 Progress and  impact of VLSI  (6pp)
		VLSI Manufacturing Process Video, Quiz 1	video	Quiz 1  read ahead of video
11	March 25	VLSI Fabrication, Packaging and Test Video, Quiz 2	video  Technology Roadmap	Quiz 2  read ahead of video
		Design Metrics (ppt)	1.3, 5.1-5.3, Design Metrics  (6pp)	Quiz 1 due
		MOS Transistor (ppt)	3.3 pp.87-106 (6pp)	Quiz 2 due
12	April 1	Static CMOS compound gates   (ppt)	6.1, 6.2 (6pp)	HW 5 due
		Transient behavior, depletion region and diffusion capacitance (ppt)	3.3-3.7 pp.106-120 (6pp)
13	April 8	CMOS inverter Characteristics, VTC, Noise Margins   (ppt)	3.3, 3.5,3.6, 3.2.4, (6pp)	HW 6 due: Ch.3 pr. 10 (30 points)
		CMOS inverter delays, fan-in fan-out, Power dissipation.    (ppt)	3.3.4, 4.1, 4.2
14	April 15	Static CMOS Design, Propagation Delay Analysis, Transistor Sizing (ppt) Design for Worst-Case, Fast CMOS Design Techniques	4.2.1 - 4.2.2  3.3.5 (6pp) 4.2.1	HW 7 due: Ch.3 pr. 17 (20 points)
		Fast Gate Design Techniques: Ratioed Logic, Pseudo NMOS, CMOS Switch Logic, Critical Path, DCVSL, Adaptive Loads, PTL, Transmission Gates, Delay Optimization, Standard Cell Layout Methodology	4.2.2, 4.2.3
15	April 22	Power Dissipation (ppt)	4.3.4, 4.5	HW 8 due
		Sequential Logic, Metastability, Timing Definitions, Static CMOS Latch (ppt),	6.1, 6.2.1 6.2, 6.3	Quiz 3 due
		Final Project Presentation - use Power Point 8-10 min per student (show architecture, final mapping, discuss simulation and test results)	Speaker Feedback Form	Quiz 3 Discussion
		Final Project demonstration in lab Designs must be mapped to the Xilinx board and tested	Format for reports	Return Final Project Reports  to  Dr. Starzyk office by April 29, 2013
	Monday, April 29, 10:10 a.m	No Final Examination	Final Exam Requirements:
		Extra reading
		ALU design Parwan slides	slides 1112.1-12.4 Xilinx University Program
		Gordon Moore (pdf)
		VLSI design methodology (ppt) Packaging (ppt)	UCB video webcast of EE 141 Digital Integrated Circuits

Notes: Chapter sections are from the text by J. M. Rabaey, A. Chandrasakasan, B. Nikolic "Digital Integrated Circuits - A Design Perspective", Prentice Hall, 2003.

K.C. Chang, "Digital Design and Modeling with VHDL and Synthesis", IEEE Computer Society Press, 1997.
Homework are due by the date indicated.

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Note:
Most of the presentation slides are adapted from "Digital Integrated Circuits - Instructor Resources" at http://bwrc.eecs.berkeley.edu/IcBook/  see also http://infopad.eecs.berkeley.edu/~icdesign, Copyright 2002 UCB.